Switched DC-DC converters comprise a switchable power stage, wherein an output voltage is generated according to a switching signal and an input voltage. The switching signal is generated in a controller that adjusts the output voltage to a reference voltage. A buck converter is shown in FIG. 1. The switched power stage 11 comprises a dual switch consisting of a high-side switch 12 and a low-side switch 13, an inductor 14 and a capacitor 15. During a charge phase, the high-side switch 12 is turned on and the low-side switch 13 is turned off by the switching signal to charge the capacitor 15. During a discharge phase the high-side switch 12 is turned off and the low-side switch 13 is turned on to match the average inductor current to the load current.
However, it is well known to power engineers that the use of switched DC-DC converters, or in general switched mode power supplies (SMPS), to achieve output voltage regulation with high efficiency has as well disadvantages. One of the most common issues is the emission of high frequency noise related to the switching activity of such power supplies that propagates to adjacent circuitry degrading their performance and often leading to failure of operation. To limit this problem, available SMPS solutions have the functionality to synchronize the switching activity to a host system or to stop the switching activity during critical system operation.
Such a synchronization feature is also advantageous in applications where a parallelization of SMPS is required so that multiphase configuration can be achieved by a synchronized operation of multiple SMPS connected in parallel and driven by a master.
Analog PWM controllers for SMPS address the problem of synchronizing the switching frequency to an external signal by tuning the frequency of an internal oscillator that controls the generation of the PWM signal. The nominal frequency of the internal oscillator can be programmed via a RC network and it can be tuned to the external reference. Although the synchronization process in an analog solution does not impact the stability of loop regulating the output voltage, it has the limitation that the synchronization may not be possible for frequencies of the oscillator too far from the external reference. Therefore, proper values of R and C of the RC network need to be chosen. Moreover, the synchronization activity affects the system clock. Thus, the frequency range of synchronization may be limited by the maximum frequency of operation of the analog circuitry.
A synchronization feature is available in digital PWM controllers as well. The nominal switching frequency of the SMPS can be selected by programming it into a register or selecting it via pin-strapping. Such a frequency in contrast to analog solutions is not affected by the tolerance of external components. The most common approach is to use an internal phase locked loop (PLL) whose frequency is locked to the external reference signal. The PLL then provides the clock signal to the digital control logic as well as to the digital PWM generator. Due to the architecture of the digital controller, controller parameters are a function of the sampling frequency of the output voltage and therefore performance of the output voltage regulation loop may be affected by the synchronization process. As well, the loss of the external reference signal may lead to oscillation of the output voltage because it affects directly the frequency of operation of the digital PWM generator.
SMPS generally regulate the output voltage Vout from input voltage Vi to a desired set point, i.e. reference voltage, by means of controlling the on-time of the high-side switch and the low side switch in a periodically with constant switching frequency Fsw. Although SMPS are developed to operate at a nominal switching frequency chosen by the user to match application requirements, there is a need to control the frequency of the switching activity in a way that the switching frequency of the SMPS is synchronous to the frequency of an external reference signal, i.e. the period and phase of the external reference signal equals the ones of the switching signal of the SMPS. However, varying the switching frequency while a SMPS is in operation may lead to oscillation on the output voltage during the synchronization phase, and, in extreme cases, to instability of the output voltage control loop itself. Hence, there is a need to control the frequency of the switching activity while the SMPS is in operation such that neither unstable closed loop operation occurs nor the performance of the controller is significantly affected. Moreover, there is a need though, to synchronize the switching frequency to an external reference signal so that, for example, a precise multi-phase operation can be achieved by connecting a plurality of SMPS in parallel or the switching frequency can be lowered to fall out of a range of frequencies that may disturb the operation of other circuitry of the SMPS.